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Frequently Asked Questions What is Dahlia? Dahlia is a typed imperative programming language for designing FPGA accelerators. It targets High-Level Synthesis toolchains such as Vivado HLS as its compilation target. Dahlia aims to reduce pitfalls of HLS programming, from simple interface issues which are not checked by vendor tools to complex and unsuspecting behavior due to interaction between different optimizations. What is predictable accelerator design? High performance HLS designs require tuning hardware optimizations such as loop unrolling, pipelining, memory banking etc.
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About
Frequently Asked Questions What is Dahlia? Dahlia is a typed imperative programming language for designing FPGA accelerators. It targets High-Level Synthesis toolchains such as Vivado HLS as its compilation target. Dahlia aims to reduce pitfalls of HLS programming, from simple interface issues which are not checked by vendor tools to complex and unsuspecting behavior due to interaction between different optimizations. What is predictable accelerator design? High performance HLS designs require tuning hardware optimizations such as loop unrolling, pipelining, memory banking etc.
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https://capra.cs.cornell.edu/dahlia/page/aboutAbout
Frequently Asked Questions What is Dahlia? Dahlia is a typed imperative programming language for designing FPGA accelerators. It targets High-Level Synthesis toolchains such as Vivado HLS as its compilation target. Dahlia aims to reduce pitfalls of HLS programming, from simple interface issues which are not checked by vendor tools to complex and unsuspecting behavior due to interaction between different optimizations. What is predictable accelerator design? High performance HLS designs require tuning hardware optimizations such as loop unrolling, pipelining, memory banking etc.
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- descriptionFrequently Asked Questions What is Dahlia? Dahlia is a typed imperative programming language for designing FPGA accelerators. It targets High-Level Synthesis toolchains such as Vivado HLS as its compilation target. Dahlia aims to reduce pitfalls of HLS programming, from simple interface issues which are not checked by vendor tools to complex and unsuspecting behavior due to interaction between different optimizations. What is predictable accelerator design? High performance HLS designs require tuning hardware optimizations such as loop unrolling, pipelining, memory banking etc.
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